1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device having a plurality of semiconductor elements and a method of manufacturing the same.
2. Description of the Related Art
Chip-on-chip type semiconductor devices have been developed as a result of technological developments in recent years. For instance, Patent Document 1 (JP-A-2006-19433; especially FIGS. 1 through 4 and 31) describes a semiconductor device having a structure where a wiring layer is supported by a silicon layer operating as support layer for supporting the wiring layer to thereby form a flat plate-shaped wiring member, a through electrode is formed in the flat plate-shaped wiring member so as to run through the wiring layer and support layer, and semiconductor elements are mounted on the opposite surfaces of the wiring member with the through electrode interposed therebetween. Here, conductor through holes that are provided to perform connection with the respective external connection terminals are buried in sealing resin that is applied so as to cover the lateral surfaces of the semiconductor element mounted on one of the surfaces of the wiring member.
Additionally, the structure of the semiconductor device disclosed in Patent Document 1 is such that the semiconductor elements mounted on the opposite surfaces of the wiring member are connected with each other by way of the through electrode and one of the semiconductor elements is mounted on an electrode forming surface where solder balls are formed as the external connection terminals.
The known semiconductor device disclosed in Patent Document 1 is manufactured in the following manner. Firstly, a semiconductor chip is mounted in a face-down manner on a wiring member formed on a support substrate and sealed by resin along with conductor through holes. The support substrate is removed after removing the sealing resin to expose the surfaces of the conductor through holes. As the support substrate is removed, the through electrode for connecting semiconductor elements with each other becomes exposed so that another semiconductor element is mounted on the through electrode in a face-down manner to produce a semiconductor device.
However, a semiconductor device disclosed in Patent Document 1 is accompanied by the following problems.
The first problem is that a silicon layer is used as the support layer in the wiring member. While silicon etching or RIE may be used to form a through electrode running through the wiring layer and support layer, the use of such a technique raises the cost of manufacturing the semiconductor device.
Additionally, the manufacturing process is complex and cumbersome to further raise the manufacturing cost. More specifically, conductor through holes for connecting with external connection terminals need to be formed on the wiring member in advance and the manufacturing step that comes after mounting semiconductor elements and sealing with resin to grind and remove the sealing resin in order to use the conductor through holes as electrodes involves a step of exposing a metal surface. Both metal and resin need to be ground at the same time in this step so that fine metal fragments can be scattered on the resin surface to give rise to short-circuiting between the electrodes.
The second problem is that a semiconductor element is mounted on the electrode forming surface where solder balls are formed as external connection terminals. When mounting such a package on a motherboard, the height of the solder balls of the external connection terminals has to be determined by taking thickness of the mounted semiconductor element into account. Then, the amount of solder needs to be increased so that by turn the diameter of the electrodes has to be raised to make it impossible to arrange terminals at a small pitch. When, on the other hand, terminals are arranged at a small pitch without increasing the amount of solder, the semiconductor element may become in contact with the motherboard to give rise to a defective connection on the part of the solder.
Additionally, while both of the two semiconductor elements are mounted so as to face down relative to the wiring member, the through electrodes located in the areas for connecting chips to each other are arranged at a fine pitch so that the high precision flip chip mounting operation has to be conducted twice to consequently reduce the manufacturing yield factor. The time that needs to be spent for alignment is inevitably long due to the high precision mounting to consequently raise the manufacturing cost.